(1) Field of the Invention
The present invention generally relates to integrated electronic circuit fabrication. More specifically, the present invention relates to a method for patterning a polysilicon gate layer.
(2) Description of the Related Art
The semiconductor industry has seen the continuous development of manufacturing processes in the fabrication of devices and circuits in ever higher density, quantity, and reliability. Although integrated circuit chip size has grown as more and more devices are crowded into circuits, higher densities may not be possible without commensurate decrease in the size of the parts of individual devices of the integrated circuit, known as device feature size. This decrease has been brought about by improvements in the imaging process--photolithography--also known by such names as photomasking, optical lithography, and microlithography.
Photolithography is a patterning process that results in removal of selected portions of added surface layers. After removal, a pattern or image of the layer is left on the wafer surface. The material removed may be in the form of a trench or hole in the layer or just a remaining line or island of the material. It is this patterning process that creates the surface parts of the devices that make up a circuit.
It is important that the dimensions of a pattern created on a wafer surface be as close to the design requirements as possible. This goal is referred to as the resolution of the images on the wafer. Patterns created on a wafer's surface near or with the exact dimensions (feature size), required by the circuit design, are considered to have high resolution and dimensional control. Patterns created on the wafer surface away from the exact dimensions required by the circuit design are considered to have poor dimensional control. Patterns having poor dimensional control can cause changes in the electrical functioning of the device or circuit. Changes in the electrical functioning of the device or circuit lead to poor transistor performance in semiconductor integrated circuits.
Conventional photolithography processes utilize photoresists--light-sensitive layers formed upon substrate, that are typically exposed to high-intensity light through a mask. The exposed or unexposed photoresist is then dissolved with developers, leaving a pattern of photoresist which allows etching, subsequently performed, to take place in some areas while preventing it in others.
However, typically in the fabrication of transistor gates, conventional photolithography processes require the use of a bulk imaging photoresist. A bulk imaging photoresist is used to function as an effective barrier during an etching step of a patterning process. Therefore, in a conventional photolithography process, selection of the thickness of the photoresist layer may be problematic due to the competing interests that the photoresist layer be thin enough to prevent as much loss of resolution as possible during an exposure step and be thick enough to function as a reliable etch barrier during the etching process.
These criteria are especially critical for developing high performance integrated circuits where it is important to scale and control the physical gate dimension of MOSFETS to obtain reduced feature size, increased circuit density, and high speed. The current demands of decreased feature sizes, especially into deep-submicron range, and increased need for high resolution images have exceeded the capabilities of the conventional photoresist processes.
It is desirable to provide a process for patterning a gate of a transistor to obtain high image resolution but yet provide good photoresistance to etching. It is desirable that such process be easily integrated into a standard CMOS fabrication process.